a) Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device having a heterojunction compound semiconductor laminated layer.
b) Description of the Related Art
There are various kinds of compound semiconductor devices having a heterojunction compound semiconductor laminated layer. For example, a heterojunction FET (HFET), including a high electron mobility transistor (HEMT), which is one kind of field effect transistors (FET) has a heterojunction at an interface between a compound semiconductor layer (two dimensional electron/hole carrier transport channel) having a relatively narrow band gap and another compound semiconductor barrier layer (in the case of HEMT, impurity doped carrier supply layer) having a relatively wide band gap.
A narrow potential valley is formed in the carrier transport channel layer adjacent the interface with the barrier layer and provides a transport channel for two dimensional electron gas (2DEG). A HEMT has a barrier layer doped with n-type impurities and a carrier transport channel which is non-doped or lightly doped with n-type impurities. Even when the barrier layer is non-doped, a carrier transport channel for 2DEG is formed. When carriers are supplied, e.g. from the source electrode, a current is allowed to flow. Although higher mobility is made possible by lowering the impurity concentration in the carrier transport layer, the carrier transport layer may be doped. Positive holes can also be used as carriers. The term "HFET" stands for HEMT-like transistors including these variations.
In forming a complementary HFET (HEMT) circuit effective for a low power consumption, generally, an n-channel carrier transport channel and a barrier layer and a p-channel carrier transport channel and a barrier layer are laminated.
In forming a transistor by using underlying semiconductor layers, upper semiconductor layers are etched. For the mass production of integrated semiconductor circuits, it is necessary to precisely control the etching amount in order to obtain uniform properties of semiconductor elements.
FIGS. 8A to 8C illustrate examples of a conventional method of manufacturing a complementary HFET which is a so-called HEMT.
As shown in FIG. 8A, an i-type GaAs layer 82, a p-type AlGaAs layer 83, an i-type GaAs layer 84, an n-type AlGaAs layer 85, and an i-type GaAs layer 86 are laminated in this order on a semiinsulating GaAs wafer 81, by metal organic chemical vapor deposition (MOCVD).
As shown in FIG. 8B, a photoresist mask 89 having an opening at a p-type HFET forming region is formed on the wafer surface. The i-type GaAs layer 86,n-type AlGaAs layer 85, and the upper region of the i-type GaAs layer 84 are etched by using an aqueous solution of H.sub.2 O.sub.2 +HF as an etchant, leaving an i-type GaAs layer 84a having a predetermined thickness. Thereafter, the resist mask 89 is removed.
As shown in FIG. 8C, a tungsten silicide WSi.sub.x layer is formed on the wafer surface and patterned by using a resist mask or the like, to thus form a gate electrode Gn for an n-type HFET and a gate electrode Gp for a p-type HFET.
Next, a resist mask having openings at ohmic electrode forming regions for the p-type HFET is formed and Be and F ions are doped through the openings. Instead of Be as a p-type impurity, Mg or the like may be used. F for increasing an impurity activation yield may be omitted.
Next, a resist mask having openings at ohmic electrode forming regions for the n-type HFET is formed, and Si ions are doped through the openings.
After p- and n-type impurities are doped, the wafer is heated to undergo activation annealing. This annealing forms an n.sup.+ -type regions 87 at the Si doped regions and a p.sup.+ type regions 88 at the Be and Fe doped regions.
Next, a resist mask having an opening for separating the n-type HFET and p-type HFET is formed, and oxygen ions are doped to form a separation region 91.
Thereafter, a resist mask having openings at the ohmic electrode forming regions of the p- and n-type HFETs is formed to vapor deposit an ohmic electrode material. After a lift-off process, alloying is performed to form source/drain electrodes S/D. For example, a stacked layer of an AuGe layer, an Ni layer, and an Au layer is used for the n-type HFET source/drain electrodes S/Dn, and a stacked layer of an Au layer, a Zn layer, and an Au layer is used for the p-type HFET source/drain electrodes S/Dp. Thereafter wirings are connected to the electrodes of the p- and n-type HFETs.
The i-type GaAs layer 82 forming the channel of the p-type HFET is separated from the gate electrode Gp by the p-type AlGaAs layer 83 and the left i-type GaAs layer 84a. The threshold voltage of the p-type HFET therefore changes with a thickness of the left i-type GaAs layer 84a. In order to obtain uniform characteristics of P-type HFETs, it is necessary to precisely control the etching amount of the i-type GaAs layer 84.
The region where the p-type HFET is formed is isotropically wet etched so that the peripheral area of this region is slanted. This slanted area is difficult to be used as device regions.
A process of etching a plurality of layers made of a plurality kind of materials is also used for manufacturing other compound semiconductor devices. However, it has been difficult to efficiently and precisely etch a heterojunction structure having a laminated layer of two or more compound semiconductor layers.